Design of an Error Tolerant Adder
- 1 Department of Electronics and Communication Engineering, Sri Ramakrishna Institute of Technology, Coimbatore, India
- 2 Department of Electrical and Electronics Engineering, SSK College of Engineering and Technology Coimbatore, India
Abstract
Problem statement: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, Error Tolerance (ET), a novel Error-Tolerant Adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain improvement in the Power-Delay Product (PDP). Conclusion/Recommendations: One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors. Delay and power are compared for various adders like RCA and CLA. It is found that ETA has high speed and less power compared to its counterparts.
DOI: https://doi.org/10.3844/ajassp.2012.818.824
Copyright: © 2012 A. N. Jayanthi and C. S. Ravichandran. This is an open access article distributed under the terms of the
Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
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Keywords
- Error-Tolerant Adder (ETA)
- Error Tolerance (ET)
- Power-Delay Product (PDP)
- Minimum Acceptable Accuracy (MAA)
- Least Significant Bit (LSB)